This invention relates to a data processor having a plurality of processing components connected in cascade.
In multimedia data processors such as a digital signal processor (DSP), various types of arithmetic processing, such as information compression encoding/decoding, filtering, and error correction, are required.
U.S. Pat. No. 5,572,453 shows a data processor suitable for TV video data signal arithmetic processing, wherein in order to switch between one type of processing and another type of processing in each of a plurality of processing units forming a single arithmetic pipeline according to a data signal flow through the processing units, a control signal for controlling such switching is transmitted or generated according to the data signal flow.
The data processor of U.S. Pat. No. 5,572,453 is available to carry out processing operations on video data signals in uninterrupted succession but unable to start a repeat processing operation a given number of times at a given timing. In addition, the conventional data processor has no sequence for automatically stopping such a repeat processing operation.